Benchmarking Design Trade-Offs in FPGA Implementations of SIMON 64/128 Cipher

Abstract The fast evolution of resource-constrained Internet of Things (IoT) devices necessitates lightweight cryptographic solutions that balance robust security with minimal hardware demands. This paper presents a comprehensive benchmarking study of FPGA-based implementations of the SIMON 64/128 block cipher, a lightweight algorithm designed by the NSA for efficient hardware realization. Three architectural strategies are evaluated on an Artix-7 FPGA: an iterative design with a precomputed key schedule (Iter-PreK), an iterative design with an on-the-fly key schedule (Iter-OTFK), and a partially unrolled design (Unrollx2) processing two rounds per clock cycle. Experimental results reveal distinct trade-offs in resource utilization, latency, throughput, and power consumption. The Iter-OTFK design reduces latency for single-block encryption by overlapping encryption rounds with key scheduling, while the Iter-PreK design achieves higher operating frequencies. For continuous data streams, where key scheduling overhead is minimized, the Iter-PreK architecture delivers a throughput of 918.4\,Mbps, and the Unrollx2 architecture achieves a peak throughput of 1421.3\,Mbps. Compared to prior studies, this work provides a novel, holistic analysis of SIMON 64/128 on modern FPGAs, offering design guidelines for optimizing lightweight cryptography in IoT applications, such as secure sensor networks and wearable devices.