Reducing Quantum Error Correction Overhead with Versatile Flag-Sharing Syndrome Extraction Circuits

Given that quantum error correction processes are unreliable, an efficient error syndrome extraction circuit should use fewer ancillary qubits, quantum gates, and measurements, while maintaining low circuit depth, to minimizing the circuit area, roughly defined as the product of circuit depth and the number of physical qubits. We propose to design parallel flagged syndrome extraction with shared flag qubits for quantum stabilizer codes. Versatile parallelization techniques are employed to minimize the required circuit area, thereby improving the error threshold and overall performance. Specifically, all the measurement outcomes in multiple rounds of syndrome extraction are integrated into a lookup table decoder, allowing us to parallelize multiple stabilizer measurements with shared flag qubits. We present flag-sharing and fully parallel schemes for the [17,1,5] and [19,1,5] Calderbank-Shor-Steane (CSS) codes. This methodology extends to the [5,1,3] non-CSS code, achieving the minimum known circuit area. Numerical simulations have demonstrated improved pseudothresholds for these codes by up to an order of magnitude compared to previous schemes in the literature.