Design and FPGA Implementation of Five Stage Pipelined RISC -V Processor

This paper describes the design and implementation of RISC-V 5-Stage pipelined processor on Basys-3 FPGA Board. The RISC-V core is based on RV32I instruction set architecture. The five-stages of pipelines are namely, instruction fetch, instruction decode, execute, memory access and write back stages with a hazard control unit which contains a stall controller. The proposed RISC-V processor is designed with a Harvard storage structure. RISC-V processor was pipelined to increase the throughput and the maximum operating frequency. For single cycle RISC-V processor maximum 31.6MHz operating frequency is achieved. The five-stage pipelined RISC-V processor is implemented on the Basys-3 board at a clock frequency of 50MHz and it had worst net slack (WNS) of 8.6ns which indicates that the maximum operating frequency can be 87.86MHz and nearly 2.78 times the maximum frequency of the single cycle processor. The power consumption also improved from 244mW to 96mW.