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The analog/radio-frequency (RF) performance of a ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET) with dielectric spacer was designed and proposed. The utilization of gate side wall spacers aims to mitigate short-channel effects (SCEs), and improve overall device performance. Simulation results demonstrate enhanced performance metrics, including improved transconductance (80%), reduced gate leakage (95.4%), and enhanced cutoff frequency (25%), making this design a promising candidate for next-generation high-performance analog and RF applications. Additionally, a novel machine learning (ML)-assisted approach is proposed for investigating the spacer-based FE-MOSFET to reduce the computational cost of numerical TCAD device simulations with the help of conventional- artificial neural network (C-ANN). This method is reported for the first-time ML-based C-ANN for Fe-based low-power MOSFET, matches the similar accuracy of physics-based TCAD with the fastest learning rate and fastest computational speed (in 95–100 s). An ML-based prediction replacement for physics-based TCAD is developed to save around 8–10 h of runtime for each iteration. Because ML predictions can never be 100% accurate, it is essential to ensure approximately zero mean-square error in the final results.
Singh et al. (Mon,) studied this question.