Sensorless Voltage-Balanced Cascaded H-Bridge Rectifier Through Submodule Parallelization

The cascaded H-bridge converter (CHBC) is the core unit that constitutes the topology of the solid-state transformer (SST), multilevel static compensator (STATCOM), etc. To maintain the voltage balance of individual submodules (SMs), the traditional software-based method requires a large number of voltage sensors, complex communication systems, and high-performance computing devices, which will lead to high complexity and cost with the increase of SM number. In this paper, a cascaded H-bridge rectifier (CHBR) with parallel connection capability is proposed, which can be used as the front stage of SST. The sensorless voltage balance is achieved in a hardware-based way. Only one switch is added to the original SM to provide additional parallel states between adjacent SMs, but the sampling, communication, and computing system can be greatly simplified. The operating analysis, modulation design, spike balance current estimation, and power loss calculation are carried out in detail. Both simulation and experimental results are provided to demonstrate the feasibility of the proposed topology and methods.