An efficient algorithm for estimating gate-level power consumption in large-scale integrated circuits

Estimating power dissipation in Very Large Scale Integrated (VLSI) circuits, particularly large-scale sequential circuits, is a significant challenge in Electronic Design Automation (EDA). Benchmarked against PrimeTime PX, the proposed algorithm proficiently analyzes large-scale combinational and sequential circuits. This research begins with a power analysis algorithm for combinational circuits, focusing on signal probability (SP) and transition count (TC). It then extends to sequential circuits, introducing methodologies for loopback issues and a validity-checking mechanism for spatial dependency topology. Developed on the OpenTimer open-source framework using the SMIC 40-nm process library, the algorithm was validated on academic and industrial datasets. Experimental evaluations show that our algorithm outperforms in terms of speed and accuracy. For power analysis with vector annotations, it achieves an average error within 0.16% in power testing of large-scale timing circuits. It also performs gate-level vectorless power analysis on complex topology and large-scale integrated circuits, demonstrating computational robustness.