In digital circuits, Double Edge Triggered Flip-Flops (DETFFs) have emerged as a crucial component, specifically in applications that necessitate precision timing. Their flexible design, which allows them to be constructed using a variety of gate logic forms such as Complementary Metal-Oxide-Semiconductor (CMOS) or Transistor–Transistor Logic (TTL), and in multiple configurations including D, JK, and T flip-flops, accentuates their ubiquity in digital circuitry. The present study seeks to augment the current under-standing of static double-edge triggered pulsed flip-flops (DETFFs) and introduces a novel structure. This proposed design incorporates cascaded pull-up and pull-down Metal-Oxide-Semiconductor (MOS) transistors for both the clock and D inputs. We simulated this new configuration at three different frequencies—50 kHz, 100 kHz, and 1 MHz—using Tanner SPICE (TSPICE), operating at a voltage of 1.3 V. Our findings reveal a significantly reduced power consumption by the proposed circuit compared to existing designs. With an improvement exceeding 95% in the Power-Delay Product (PDP), this proposed DETFF emerges as a promising contender for implementation in low voltage, low power digital circuits. The substantial PDP improvement and the power efficiency of our proposed DETFF design underscore its potential in revolutionizing low-power digital circuit design. Thus, this work concentrates on modelling an Energy-Efficient Unequal Cluster Management using the Elephant Herd Optimization approach (EEUCM-EHO) that considers the distance explicitly to reduce energy consumption. The maximal nodes transmission ability is provided with higher significance using the clustering strategy of EHO. Moreover, EEUCM-EHO concentrates on clustering strategies. The anticipated EEUCM-EHO is evaluated with various performance metrics like average energy consumption, network lifetime, average residual energy, and the number of alive nodes.
Ashok et al. (2025) studied this question.