Wafer warpage poses a significant challenge to thin-film uniformity for silicon oxide (SiO2) film deposited by plasma-enhanced chemical vapor deposition (PECVD), critically impacting semiconductor device performance and yield. This work elucidates the underlying mechanism by which warpage disrupts deposition, primarily through the distortion of radio frequency (RF) impedance matching and plasma spatial distribution. We present a coupled simulation-experimental approach to investigate this phenomenon. Finite element method simulations revealed that warpage-induced variations in the wafer-heater gap cause localized electric field intensification and plasma non-uniformity. Experimental results demonstrated that severe warpage (180 μm) under insufficient preheating (15 s) led to significantly low-frequency reflected power fluctuations (up to 89.1% amplitude ratio), indicating severe impedance mismatch. Critically, we identify and optimize preheating time as an effective in-situ compensation strategy. Extending the preheating duration to an optimal 100 s suppressed reflected power disparity by up to 60% and dramatically enhanced film thickness uniformity by over 80% for 100 μm-warped wafers. The observed non-monotonic relationship between preheating time and process stability is discussed in the context of dynamic thermoelastic stress evolution within the wafer. This study provides both fundamental insights into plasma-wafer interactions under geometric distortion and a practical, thermally-based strategy for enhancing PECVD process robustness in advanced semiconductor manufacturing.
Li et al. (Thu,) studied this question.