Abstract Robust, tightly localized photonic modes are essential for scalable on-chip quantum information processing, including multi-plane (3D-integrated) photonic platforms in which multiple planar waveguide layers are vertically stacked and coupled. Here, we present a comprehensive study of three three-dimensional fractal photonic architectures, 3D Cantor dust, Vicsek fractal, and Sierpinski sponge, each discretized into dielectric voxels and modeled in a voxel-graph tight-binding surrogate with exponentially decaying evanescent-hopping couplings. We examine two imperfection classes: on-site refractive-index disorder (amplitude up to 10%) and stochastic voxel deletions (defect rate up to 2%). In a classical eigenanalysis (over 10 000 parameter combinations of waveguide width, layer thickness, baseline coupling, decay constant, and defect rate) we compute the central spectral spacing Δ λ (a finite-structure stopband proxy) and the inverse participation ratio, and demonstrate via ANOVA/Tukey HSD (adjusted p 10^-3 p ≪ 10 - 3) that 3D Cantor dust yields the largest mean central spacing and highest inverse participation ratio across depths and parameter ranges. Because the canonical Cantor-dust voxelization is disconnected under the unit-neighborhood coupling rule used in this paper, its high IPR should be interpreted as isolation-dominated localization within this surrogate. We additionally map the tight-binding coupling graphs to 2-local qubit Hamiltonians in the single-excitation manifold (one qubit per retained site), and we validate a variational quantum eigensolver workflow on a 2-qubit SSH dimer and on 4–8-qubit fractal subgraphs; the qubit counts, optimization objective, shot-based measurement model, and resource scaling with fractal iteration depth are stated explicitly. Our work positions 3D Cantor dust as a favorable multi-scale platform for graph-spectral stopband engineering and robust mode localization in tight-binding surrogates, motivating targeted full-wave electromagnetic validation and device-level studies of planar-mask implementations (stacked 2D fractal layers with vertical couplers) for 3D-integrated on-chip deployment.
Villalba-Díez et al. (Wed,) studied this question.