What question did this study set out to answer?

This analysis aims to identify the causes of line edge roughness in manufacturing integrated circuits and explore methods for its reduction.

March 26, 2026

Analysis of the Causes of the LER Effect and Methods for Reducing Its Magnitude

Key Points

This analysis aims to identify the causes of line edge roughness in manufacturing integrated circuits and explore methods for its reduction.
Comprehensive analysis of line edge roughness sources in the photolithographic process.
Identification of mechanisms transferring defects to nanostructure topology.
Correlation analysis between lithography, etching parameters, and IC dimensions.
Discussion of technological solutions for controlling LER.
Identified key factors contributing to line edge roughness during photolithography.
Demonstrated the impact of lithography and etching on final dimensional accuracy.
Outlined several promising technological methods for reducing LER effectively.

Abstract

This paper presents a comprehensive analysis of the sources of line edge roughness (LER) and strategies for its reduction in integrated circuit manufacturing. The main factors causing LER in the photolithographic process and the mechanisms of transferring this defect to the topology of nanostructures are identified. The correlation between the parameters of lithography, etching processes, and the final linear dimensions of IC elements is analyzed. The article discusses promising methods and technological solutions for controlling and reducing LER.

Analysis of the Causes of the LER Effect and Methods for Reducing Its Magnitude

Key Points

Abstract

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