Endurance Paradox in Hafnium-Oxide-Based Silicon-Channel Ferroelectric Transistors

program/erase cycles. Here, we show that this loss of device functionality is not caused by intrinsic degradation of the ferroelectric layer. By examining the same electrically degraded gate stack after memory-window closure, we find that robust polarization switching is still preserved, demonstrating that the ferroelectric medium remains functional, even when transistor-level memory operation has collapsed. The origin of failure instead lies at the interface, where charge trapping and the associated electrostatic screening progressively reduce the threshold-voltage contrast between the programmed states. As a result, the device loses its ability to operate as a memory transistor even though the underlying ferroelectric stack continues to switch. These findings provide direct evidence that endurance in hafnium-oxide-based ferroelectric transistors is governed primarily by interface degradation rather than by true ferroelectric fatigue.