Designing computing systems for safety-critical platforms operating in harsh environments now demands balancing high computing performance with reliability and low-power execution. In New Space missions, for instance, Commercial Off-The-Shelf (COTS) devices are used as an alternative to Radiation Tolerant (RT) FPGAs and Radiation Hardened By Design (RHBD) ASICs, sacrificing reliability over pure computing power. Nevertheless, a bare minimum fault tolerance level needs to be ensured in order to successfully run the missions. Depending on the target fabric, multiple mitigation techniques can be implemented at the technology node, microarchitecture or system level. These mechanisms are typically complemented with intensive fault-injection and beam testing campaigns. Open Instruction Set Architectures (ISAs), like RISC-V, free from proprietary licensing constraints, allow controlled architectural variation across both COTS FPGA and ASIC fabrics, enabling easier fault injection/beam studies and Power-Performance-Area (PPA) analysis for competitive design development. This paper presents an open-source architectural template for accelerator deployment in safety-critical systems. The template, built around a triple-core RISC-V platform, integrates system-level reliability techniques that enable runtime-adaptive switching among Single, Triple-Core LockStep (TCLS), Dual-Core LockStep (DCLS), and DCLS with classical staggering modes. The template has also support for application-specific, hardware-based functional extensions, either via memory-mapped interfaces or through custom ISA extensions (attached to each of the triplicated cores using the standard CORE-V eXtension Interface). The capabilities of the proposed accelerator template have been tested both with a software-only implementation of the AES-128 data encryption algorithm and with an in-house implementation of the CCSDS 121 data compression algorithm, widely used in space applications, showing that the system-level reliability techniques can be straightforwardly extended to the hardware-accelerated functions as well. The assessment of the proposed accelerator template includes experimental evaluation of the reliability through a lightweight fault injection campaign, and both FPGA and TSMC 65 nm LP implementations.
Waucquez et al. (Fri,) studied this question.