Calculating worst-case gate delays due to dominant capacitance coupling

In this paper we develop a gate level model that allows us to determine the best and worst case delay when there is dominant interconnect coupling. Assuming that the gate input windows of transition are known, the model can predict the worst and best case noise, as well as the worst and best case impact on delay. This is done in terms of a Ceff based gate model under general RC interconnect loading conditions. I. INTRODUCTION As IC dimensions scale to the deep submicron range, their multi-level interconnects are constructed such that the coupling capacitance becomes the dominant component of load capacitance. This effect is largely the result of the increased ratio between the lateral and the vertical capacitance of the line. The increased number of metal layers is the other source of coupling capacitance problems, since there is a reduced likelihood of a nearby ground plan. The lateral capacitance is increased by the relative increase in the metal thickness with respect to line sp...