Oxide thin-film transistors (TFTs) have shown great promise for monolithic 3D integration with silicon chips through back-end-of-line (BEOL) processes. While BEOL processing involves high-temperature (350–400 °C) thermal steps that are generally beneficial for n-type oxide TFTs, such conditions pose a critical challenge for p-type SnO TFTs, where high temperatures commonly induce high n-type conduction and pronounced degradation of the on/off current ratio. This study revealed that post-annealing at elevated temperatures induces the disproportionation of SnO into Sn0 and Sn4+ species, which contributes to the rise in electron current in SnO TFTs. To address this challenge, we first introduced Pt(O)/Pt electrodes with an Al2O3 interlayer to form Schottky drain contacts for blocking electron injection. More importantly, a submicrometer gate-to-drain (G–D) gap was designed to enhance electron depletion near the drain under negative drain bias, and simulations confirmed that the G–D gap modulates the electrostatic potential and carrier distribution. The combined strategy not only effectively suppressed ambipolar channel conduction after annealing at 385 °C but also reduced electron current by over three orders of magnitude without sacrificing the p-type on-current, underscoring the potential of p-type oxide TFTs for BEOL-compatible CMOS applications.
Song et al. (Mon,) studied this question.