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In this paper we study tradeoffs between energy dissipation and delay in battery-powered digital CMOS designs. In contrast to previous work, we adopt an integrated model of the VLSI circuit and the battery sub-system that powers it. We show that accounting for the dependence of battery capacity on the average discharge current changes shape of the energy-delay trade-off curve and hence the value of the operating voltage that results in the optimum energy-delay product for the target circuit. Analytical derivations as well as experimental results demonstrate the importance of correct modeling of the battery-hardware system as a whole and provide a more accurate basis for comparing various low power optimization methodologies and techniques targeted toward battery-powered electronics.
Pedram et al. (Fri,) studied this question.
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