Estimating the area, delay, and leakage power of standard cell-based FPGA tiles is challenging because synthesis optimizations create non-uniform cell composition and technology-dependent implementation effects. Traditional estimators rely on detailed transistor-level modeling or handcrafted analytical assumptions, which are costly to adapt across process technologies. Learning-based estimators can reduce this cost, but strong tabular models often require substantial training data and hyperparameter tuning. In this work, we evaluate TabPFN, a transformer-based probabilistic few-shot learning model, for predicting FPGA tile metrics directly from architectural parameters. We compare TabPFN with three tuned gradient-boosting baselines, XGBoost, LightGBM, and CatBoost, on 1,724 synthesized FPGA tile configurations across four process nodes. The results show that TabPFN achieves competitive error margins in both scarce and sufficient training data conditions across all five target metrics. The findings indicate that TabPFN is a practical option for rapid early-stage FPGA design-space exploration when labeled synthesis data is limited.
Al-Qawasmi et al. (Mon,) studied this question.