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I discuss the tradeoffs faced when asynchronous pulse trains are transmitted among large, two-dimensional, arrays of neurons on different chips, using time-division multiplexing, and present an implementation of an arbitered, random-access, channel. The long cycle time that plagues channels is addressed in the implementation described here by pipelining. Cycle times ranging from 420ns to 730ns were achieved, for 64 x 64 arrays, in a 2µm CMOS process, yielding a peak throughput of 2. 38M /second.
Kwabena Boahen (Wed,) studied this question.
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