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A highly linear input buffer is crucial for high-speed and high-resolution analog-to-digital converters (ADCs) since it isolates the kickback noise and package inductance. Several important factors affecting the linearity of the input buffer are analyzed in this brief, and a wideband input buffer with high linearity based on cascade complementary source follower (CCSF) is proposed. This cascaded input buffer is composed of a pMOS source follower (PSF) and an nMOS source follower (NSF). Compensation capacitor, assisted operational amplifier (opamp), bootstrapped-capacitor level-shifting circuit, current amplifier, and optimization strategies are utilized to extend the bandwidth and reduce distortion. Designed in a 65-nm CMOS, the CCSF input buffer achieves the spurious-free dynamic range (SFDR) and a signal-to-noise and distortion ratio (SNDR) of 76. 6 and 58. 1 dB with 1. 9-GHz input frequency, respectively. It occupies 0. 0155 mm ² and consumes 27 mW at 2. 5 V.
Li et al. (Fri,) studied this question.