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Vertical gate-all-around (V-GAA) represents the ultimate configuration in the forthcoming transistor industry, but it still encounters challenges in the semiconductor community. This paper introduces, for the first time, a dual-input logic gate circuit achieved using 3D vertical transistors with nanoscale sub-20-nm GAA, employing a novel technique for creating contacts and patterning metallic lines at the bottom level without the conventional lift-off process. This involves a two-step oxidation process: patterning the first field oxide to form bottom metal lines and then creating the gate oxide layer on nanowires (NWs), followed by selective removal from the top and bottom of the nanostructures. VGAA-NW transistors, fabricated using the lift-off-free approach, exhibit improved yield and reduced access resistance, leading to an enhanced drive current while maintaining good immunity against short-channel effects. Finally, elementary two-input logic gates within a single cell, using VNW transistors, demonstrate novel possibilities in advanced logic circuitry design and routing options in 3D.
Kumar et al. (Mon,) studied this question.