What type of study is this?

This is a Experimental Study study.

October 23, 2025Open Access

Fault tolerant and quality of service aware routing algorithm based on priority technique for scalable network on chip architectures

XYXiaomo YuGuangxi University LTLing TangGuangxi University JMJie MiHunan University of Science and Technology

Key Points

Average delay is reduced by ~8–12% and throughput increased by ~2–5% compared to traditional routing methods.
Employing multi-criteria decision-making, the algorithm adapts to link failures and ranks alternative paths based on performance.
The implementation on 16 × 16 meshes sustains low overhead and operates effectively under various disturbances.
This approach enhances fault tolerance and scalable performance, making it suitable for next-generation network on chip designs.

Abstract

Abstract Network on Chip (NoC) architectures are essential subsystems for on-chip communication. They use routers and simplified protocols modeled after public data networks to transport packets using complex routing algorithms from their source to their destination. Reliable communication can be severely hampered by component failures, such as malfunctioning routers or cables, which can interrupt packet transfer. Performance may be harmed by the narrow criteria used by traditional fault-tolerant routing algorithms to find reliable routes. In order to improve routing reliability and Quality of Service (QoS) in scalable NoC architectures, this paper suggests a novel, adaptive fault-tolerant routing algorithm that incorporates the Technique for Order of Preference by Similarity to Ideal Solution (TOPSIS), a multi-criteria decision-making technique. The suggested approach dynamically assesses and ranks alternate routes to choose the best ones, even when there are failures, by utilizing path length and density information from nearby nodes. On 8 × 8 meshes with 10% link failures, the approach reduces average delay by ~ 8–12% compared to EDAR and increases throughput by ~ 2–5% compared to EDAR; on application-driven traces, it reduces delay by ~ 5–15% at nearly equal throughput. It reduces energy per flit by around 15–20% compared to EDAR, improves throughput by about 3–4%, and lowers delay by about 8–10% under transient, thermal, and voltage disturbances. The two-stage decision core maintains the improvements on 16 × 16 meshes and reroutes locally in about 3–5 cycles without adding a critical-path cost. Additionally, the approach ensures scalability for large-scale NoC implementations by introducing low hardware overhead. The suggested algorithm is a viable answer for next-generation NoC designs, meeting the requirements of high-performance, dependable, and scalable on-chip communication systems thanks to its combination of fault tolerance, QoS awareness, and resource efficiency.

اسأل الذكاء الاصطناعي

Bookmark

View Full Paper