This paper presents a column-parallel adaptive-gain single-slope (SS) analog-to-digital converter (ADC) for high-speed high-dynamic-range (HDR) CMOS image sensors. Conventional adaptive-gain approaches often rely on dual-ramp generation or duplicated column circuits, which increase area and power overhead. In contrast, the proposed architecture achieves adaptive-gain operation using a single global ramp shared across all columns. A reconfigurable capacitive attenuation network embedded inside each column comparator locally scales the ramp at the comparator input, enabling seamless transition between high-gain operation for low-level signals and unity-gain operation for large signals within a single exposure and readout cycle. To suppress mode-dependent offsets while maintaining low noise, a configurable dual-source-follower ramp buffer symmetrically buffers the ramp and reference voltages during auto-zeroing and is reconfigured as a full-sized buffer during unity-gain conversion. Switching-induced column offsets are compensated using optical black pixels and lightweight digital processing. The ADC is implemented in a 110 nm CMOS image sensor process and validated through post-layout simulations including extracted parasitics and Monte Carlo mismatch analysis. The core ADC consumes 36.8 µW per column. Simulation results demonstrate linearity error below 1% without missing codes and show that the proposed AGx8-to-AGx1 configuration extends the effective dynamic range up to 78.3 dB.
Yoo et al. (2026) studied this question.