Grain boundaries are among the most influential structural features that control the charge transport in polycrystalline organic semiconductors. Acting as both charge trapping sites and electrostatic barriers, they disrupt molecular packing and introduce energetic disorder, thereby limiting carrier mobility, increasing threshold voltage, and degrading the stability of organic thin-film transistors (OTFTs). This review presents a detailed discussion of grain boundary formation, their impact on charge transport, and experimental strategies for engineering their structure and distribution across several high-mobility small-molecule semiconductors, including pentacene, TIPS pentacene, diF-TES-ADT, and rubrene. We explore grain boundary engineering approaches through solvent design, polymer additives, and external alignment methods that modulate crystallization dynamics and domain morphology. Then various case studies are discussed to demonstrate that optimized processing can yield larger, well-aligned grains with reduced boundary effects, leading to great mobility enhancements and improved device stability. By offering insights from structural characterization, device physics, and materials processing, this review outlines key directions for grain boundary control, which is essential for advancing the performance and stability of organic electronic devices.
He et al. (Wed,) studied this question.