Nonlinear Analysis of the Synchronous Reference Frame Phase-Locked Loop Under Unbalanced Grid Voltage

The synchronous reference frame phase-locked loop (SRF-PLL), also called dqPLL, is an electric circuit commonly used in power electronics to estimate the phase angle of a three-phase AC grid. If the voltage is unbalanced, the PLL is modeled as a periodically forced nonlinear oscillator and is known in practice to converge to a steady oscillation. In the existing literature, the oscillation has been studied via linearization assuming a low level of unbalance. Aiming for stronger nonlocal statements, we present nonlinear analysis. We apply the method of autonomous comparison systems and incremental stability to show that the steady oscillation is unique and attractive in a wider neighborhood. Its lock-in domain is estimated using numerical phase portrait analysis. The oscillation is further approximated up to the terms of the second order in the unbalance factor – it yields an estimation of the time average of the PLL’s phase error which is not visible by linearization only. The results provide stability guarantees and can guide the tuning of SRF-PLL.