Los puntos clave no están disponibles para este artículo en este momento.
Planar silicon nanowires (SiNWs), grown by using low temperature catalytic approaches, are excellent 1D channel materials for developing high-performance logics and sensors. However, a deterministic position and size control of the metallic catalyst droplets, that lead to the growth of SiNWs, remains still a significant challenge for reliable device integration. In this work, we present a convenient but powerful edge-trimming catalyst formation strategy, which can help to produce a rather uniform single-row of indium (In) catalyst droplets of Dcat = 67 ± 5 nm in diameter, with an exact one-droplet-on-one-step arrangement. This approach marks a significant achievement in self-assembled catalyst formation and offers a foundation to attain a reliable and scalable growth of density SiNW channels, via an in-plane solid–liquid–solid (IPSLS) mechanism, with a uniform diameter down to Dnw = 35 ± 4 nm, and do not rely on high-precision lithography techniques. Prototype SiNW-based field effect transistors (FETs) are also fabricated, with a high Ion/Ioff current ratio and small subthreshold swing of >107 and 262 mV·dec–1, respectively, indicating a reliable new routine to integrate a wide range of SiNW-based logic, sensor, and display applications.
Cheng et al. (Mon,) studied this question.
Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context: