Neuromorphic Computing for Energy-Efficient Edge Intelligence

Spiking Neural Networks (SNNs) have gained significant attention as an energy-efficient machine learning solution. With growing interest in the SNN algorithms, it is mandatory to understand the overheads of SNNs when implemented on real hardware accelerators. Most SNN training works are algorithm-focused and estimate the energy-efficiency of SNNs with metrics such as spike data sparsity (i.e., higher data sparsity equals higher energy-efficiency). However, sparsity is not a valid metric to claim energy-efficiency in real hardware. In this talk, I will delve into the hardware perspective of SNNs when implemented on standard CMOS and compute-in-memory (CiM) accelerators with our recently proposed SATA and SpikeSim tools. It turns out that the multiple timestep computation in SNNs can lead to extra memory overhead and repeated DRAM access that annuls all the compute-sparsity related advantages. I will highlight some techniques such as, early time-step exit as well as neural architecture search that use the temporal dimension in SNNs to reduce the overhead. Finally, I will discuss an algorithm-hardware co-optimization technique to manage non-idealities in CiM hardware to yield best hardware-level performance-and-energy efficiency tradeoffs in presence of circuits/device noise.