Design and Analysis of RNS based Montgomery multiplier using FinFET Technology

This article describes the design and analysis of RNS based Montgomery multiplier. The proposed design harness FinFET technology for low power and delay applications. Variations in VLSI design parameters lead to differences in important features such as area, power, and delay. Digital multipliers are the main source of power dissipation in any digital system. A key component of many arithmetic operations and digital signal processing applications is the digital multiplier. Generally, any multiplication scheme requires lot of power for the computation. However, Montgomery multiplier is very beneficial for secure data communication and cryptography applications as an efficient algorithm. This work presents an investigation of the Montgomery multiplier in various FinFET configurations. Moreover, the design of Montgomery multiplier is realized with various configuration methods and the concept of the sizing. And broadly studied the concept of sizing of the multiplier scheme. This work instigated and broadly considered the perceptions of sizing and optimum selective of the conformations. For the representative purpose the Residue Number System (RNS) based approach for implementing Montgomery multiplier has been preferred. The proposed design has been compared with different technology such as 45nm, 32nm and 16 nm. The library file for the various technology has been taken from Predictive Technology Model (PTM). The design implementation is performed in CADENCE EDA tool.