PANEL: EDA Challenges at Advanced Technology Nodes C

EDA ecosystem's fantastic supports and innovations have helped achieve better logic, memory, wafer-level packaging, and AI chips and systems 1 2 and 3, for decades. We look forward to the continuous win-win collaborations among university scientists, circuit designers, semiconductor chip manufacturers and EDA companies in the foreseeable future. The critical issue in 2024 is what the major challenges are. A few months ago in the December 2023 IEDM in San Francisco, world-wide semiconductor experts are postulating that the complexities of the upcoming high-end electronic systems will soon be in the range of one trillion transistors. Advanced transistors used are either FinFET or GAA/nanosheet, or both, in need of design and technology co-optimization (DTCO). Innovations in the 3DFabric Alliance 2 are essential to the trillion-transistor trend. The leap from traditional SoC/IC designs to 3DFabric (3DIC) designs brings new benefits and opportunities. This new system-level design paradigm inevitably introduces new EDA challenges on system design, verification, thermal management, mechanical stress, and electrical-photonic compliance of the entire 3DIC assembly and reliability.