A 10-bit 100-MS/s pipelined-SAR ADC with calibration-free time quantizer based on voltage-to-cycle self-aligned TDC

Puntos clave

• Achieving a high performance of 100-MS/s, this ADC showcases an innovative design approach.
• With a calibration-free time quantizer, it simplifies the ADC structure, enhancing overall efficiency.
• The design employs voltage-to-cycle self-aligned TDC for effective time quantization.
• Observations suggest that this calibration-free method could lead to significant advancements in high-speed data acquisition.