In this paper, we propose a novel soft detrap scheme to mitigate the read-after-write-delay (RAWD) issue in 3D ferroelectric (FE) NAND flash memory, while remaining compatible with current NAND array architectures. Unlike previous detrap studies limited to the single cell-level, this work investigates array-level operation mechanisms for the first time. We conducted Sentaurus TCAD simulations using a gate-injection type metal-insulator-FE-insulator‑silicon (MIFIS) 3D FE-NAND array structure, comparing two low threshold voltage (LVT) formation schemes, the page-level LVT formation (P-LVT) and the gate induced drain leakage (GIDL) based block-level LVT formation (B-LVT) schemes. Our analysis indicates that B-LVT scheme experiences more severe RAWD and on-current degradation compared to the P-LVT scheme. This is primarily due to the distribution of channel-injected interface trap charges (Q it ) along the entire string. To mitigate this issue, we propose a soft detrap scheme that applies 6 V and 1 V to the bit line (BL), common source line (CSL) and string select line (SSL) and the ground select line (GSL) immediately after the B-LVT scheme. This approach accelerates detrapping of unstable Q it and reduces RAWD from approximately 1 s to just a few microseconds, demonstrating an effective array-level operation method for reliable low voltage 3D FE-NAND. • Unstable trapped charges cause severe read delay in 3D ferroelectric NAND arrays. • A new soft detrap bias scheme effectively eliminates these unstable trapped charges. • Optimized bias selectively removes unstable charges while preserving polarization. • Delay is reduced to 4 microseconds, recovering current and memory window.
Lee et al. (Mon,) studied this question.