We introduce the Cascaded Transistor n-ary Encoding (CTnE) framework, a novel computational paradigm that achieves multi-valued (n-ary) logic encoding on unmodified conventional binary CMOS substrates. The central insight is elegantly simple yet profoundly consequential: by cascading k standard binary transistors---connecting the drain (output) of transistor i to the source (power supply rail) of transistor i+1---one obtains a composite cell capable of representing 2ᵏ - (2ᵏ - (k+1) ) = k + 1 distinguishable logical states when dead states are excluded, or, more precisely, up to 2ᵏ states in the full configuration space. We prove that a cascade of k = ₂ n transistors suffices to encode n-ary logic, and we demonstrate that the resulting cascade cells can be tiled identically to standard binary cells, thereby establishing that any existing binary processor can, in principle, execute n-ary encoded computation through purely architectural reconfiguration at the gate level without requiring novel semiconductor materials, exotic device physics, or non-standard fabrication processes. We provide rigorous mathematical foundations including a complete state-space algebra, formal encoding and decoding functions, proofs of information density gain, a complexity-theoretic analysis demonstrating exponential acceleration for classes of problems whose natural representation is non-binary, and detailed circuit-level schematics for ternary (n=3), quaternary (n=4), and general n-ary cascade cells. The implications span processor architecture, memory hierarchy design, machine learning accelerators, cryptographic systems, and quantum-classical hybrid interfaces. This work constitutes a foundational contribution to multi-valued logic implementation theory and opens a direct, immediately realizable pathway to n-ary computation on the installed base of binary silicon infrastructure worldwide.
Kaoru Aguilera Katayama (Thu,) studied this question.