Multiplication is a fundamental arithmetic operation widely used in digital signal processing (DSP), artificial intelligence (AI), and high-performance computing systems. However, conventional multiplier architectures suffer from significant limitations such as high power consumption, increased propagation delay, and large hardware complexity. To overcome these challenges, this paper presents an optimized 16-bit approximate multiplier based on advanced 5:2 compressor architectures for efficient partial product reduction. The proposed design introduces approximation in the reduction stage to minimize critical path delay and power consumption. Furthermore, an importance-driven hybrid compression strategy is employed, where accurate and approximate compressors are selectively utilized based on bit significance. Mathematical models are incorporated to evaluate error characteristics and performance trade-offs. Simulation results demonstrate that the proposed multiplier achieves improved delay, reduced LUT utilization, and lower power consumption compared to traditional 4:2 compressor-based designs. Hence, the architecture is well suited for error-resilient applications such as image processing and machine learning. (Concept adapted from recent works 15–18).
ijesat (Sat,) studied this question.