The growing demand for high-bandwidth and low-latency electronic systems has brought silicon interposers to the forefront of advanced packaging solutions. Their dense interconnects and high operating frequencies induce several Signal Integrity issues with complicated design phases. To date, Signal Integrity assessment is accomplished with EM simulations and eye diagram extractions, which are time-consuming and require high computational resources. In this thesis, the acceleration of Signal Integrity assessment with hierarchical approaches is presented, splitting large interposers into smaller, more manageable structures for the simulators, keeping the accuracy of the results at acceptable levels. Moreover, Machine Learning and Deep Neural Networks are integrated to the Signal Integrity assessment flow, in order to predict eye diagram metrics faster, with reduced computational demands. A Random Forest Regression model is used to predict three eye diagram metrics of a silicon interposer channel (Max eye height, Max Eye Width, Height at 50% of the Unit Interval of the eye) with a Mean Absolute Percentage Error of 9.26%. A second Deep Neural Network model achieved even better performance with a Mean Absolute Percentage Error of 4%, accelerating the Signal Integrity assessment with eye diagrams to tens of milliseconds.
Αλέξανδρος Ν. Χατζής (Wed,) studied this question.
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