The intersection of TinyML and reconfigurable computing forms the foundation of a hardware-accelerated architecture proposed in this paper for offline voice command recognition in smart home control applications. Eliminating dependence on cloud connectivity while meeting the strict power and latency demands of embedded systems represents the central problem this work tackles. To characterize speech signals, Mel-Frequency Cepstral Coefficient (MFCC) extraction is employed, producing a perceptually informed feature representation that lowers input dimensionality while retaining strong discriminative capability. Under TinyML design principles, a lightweight Multilayer Perceptron (MLP) is trained to classify these extracted features into a set of predefined voice commands. To minimize parameter storage and reduce arithmetic overhead, post-training quantization to 8-bit fixed-point precision is applied, making the model suitable for direct deployment on a Virtex-5 FPGA. Pipelined multiply–accumulate operations are efficiently handled by on-chip DSP slices, while Block RAM (BRAM) provides deterministic and reliable weight storage. Functional verification of each hardware module is carried out using ModelSim simulation, with synthesis and place-and-route performed within the Xilinx ISE environment. The results demonstrate that the proposed accelerator delivers low-latency, privacy-preserving recognition of short voice commands, with overall hardware resource consumption remaining comfortably within the platform's available limits.
Anil et al. (Fri,) studied this question.