An Analog Neural Network Processor With Programmable Network Topology

A neural network chip with programmable architecture contains 4096 synapses which can be programmed to form neurons with 16 to 256 weights. The datapath is best suited for convolutional architectures, such as time-delay or feature-extraction networks, but can also be configured for fully connected or feedback topologies.1.2 Computations are performed with 6b accuracy for the weights and 3b for the states. These values have been determined by simulation to be compatible with the needs of many pattern-classification applications. The chip uses analog processing internally for high density and reduced power dissipation, but all input/output is digital to simplify system integration. The circuits are designed to guarantee chip-to-chip matching across different wafer lots without trimming. The chip operates at a sustained rate of 5GC/s (5xl09 connection updates per second). The features are summarized in Table 1.