A new digital-pixel architecture for CMOS image sensor with pixel-level ADC and pulse width modulation using a 0.18 /spl mu/m CMOS technology

In this paper, a digital pixel architecture with pixel-level ADC based on Pulse Width Modulation (PWM) scheme and an 8-bit DRAM is proposed to operate at an extremely low voltage environment, i.e., 1.2 V. This digital pixel architecture is designed to eliminate the restriction of low supply voltage imposed by device scaling trend. The pixel is implemented in a commercially available 0.18 /spl mu/m, single poly and 6 metal CMOS process. Simulation results show that the circuit is functional at a V/sub DD/ of 1.2 V with a higher dynamic range and lower power consumption as compared to conventional CMOS APS architecture.