A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation

This paper reports on the design of a phase-locked-loop (PLL) for on-chip clock generation for a high-performance microprocessor (/spl mu/P). The power consumption of the /spl mu/P has been reduced by scaling down the supply voltage. The whole system has been implemented using a 0.35/spl mu/m CMOS process that features low-threshold voltages for MOS devices to maintain the speed performance. The /spl mu/P can be set in idle mode to further reduce the overall power consumption. To allow fast recovery from the /spl mu/P idle mode, the PLL runs continuously during this mode. Therefore, the power consumption of the PLL has to be minimized. To obtain the highest performance from the /spl mu/P, the output jitter of the PLL has to be as low as possible. The power switching noise generated by the running /spl mu/P directly affects the output jitter of the on-chip PLL. In summary, the challenge was to design a PLL which combines limited jitter, low-supply voltage and low-power consumption.