A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements

A 64Mb SRAM macro is fabricated in a 32nm high-k metal-gate (HKMG) SOI technology (Greene et al., 2009). Figure 14.1.1 shows the 0.154μm 2 bitcell (BC). A 2x size reduction from the previous 45nm design (Pilo et al., 2008) is enabled by an equal 2x reduction in BC area. No corner rounding of BC gates allows tighter overlay of gate electrode and active area. The introduction of HKMG provides a significant reduction in the equivalent oxide thickness, thereby reducing the Vt mismatch. This reduction allows aggressive scaling of device dimensions needed to achieve the small area footprint. A 0.7V VDD MIN operation is enabled by three assist features. Stability is improved by a bitline (BL) regulation scheme. Enhancements to the write path include an increase of 40% of BL boost voltage. Finally, a BC-tracking delay circuit improves both performance and yield across the process space.