A statistical optimization-based approach for automated sizing of analog cells

This paper presents a CAD tool for automated sizing of analog cells using statistical optimization in a simulation based approach. A nonlinear penalty-like approach is proposed to define a cost function from the performance specifications. Also, a group of heuristics is proposed to increase the probability of reaching the global minimum as well as to reduce CPU time during the optimization process. The proposed tool sizes complex analog cells starting from scratch, within reasonable CPU times (approximately 1 hour for a fully differential opamp with 51 transistors), requiring no designer interaction, and using accurate transistor models to support the design choices. Tool operation and feasibility is demonstrated via experimental measurements from a working CMOS prototype of a folded-cascode amplifier.