A Programmable and FPGA-accelerated GTP Offloading Engine for Mobile Edge Computing in 5G Networks

This poster presents a programmable and FPGA-accelerated packet processing engine, performing the encapsulation and decapsulation of GPRS Tunneling Protocol (GTP) packets, for Mobile Edge Computing in 5G Networks. The proposed engine is designed by using the P4 language and is implemented to the FPGA platform by using the Xilinx SDNet tool. The implemented system is practically realized on the Xilinx FPGA platform and the detailed architecture is presented. The experimental results show that targeted throughput of 10Gbps per port is achieved given the packet-processing latency of 5μs.