On modeling and analyzing cache hierarchies using CASPER

The efficient use of cache hierarchies is crucial to the performance of uni-processor (desktop) and multiprocessor (enterprise) platforms. A plethora of research exists on the various structures and protocols that are of interest when considering caches. To enable the performance analysis of various cache hierarchies and associated allocation/coherence protocols, we developed a trace-driven simulation framework called CASPER - cache architecture simulation a brief overview of some of these CASPER-based evaluation studies and their salient results will also be discussed. Based on its wide-ranging applicability, we believe CASPER is a useful addition to the performance analysis community for evaluating cache structures and hierarchies of various kinds.