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A static VAr compensator (SVC) model based on state variable techniques is presented. This model is capable of being interfaced to a parent (or host) electromagnetic transients program, and, in particular a stable method of interfacing to the EMTDC program is described. The model is primarily that of a thyristor-controlled reactor. (TCR) and a thyristor-switched capacitor (TSC). Capacitor switchings within the TSC have been handled in a novel way to simplify storage and computation time requirements. During thyristor switching, the child SVC model is capable of using a smaller timestep than the one used by the parent electromagnetic transients program; after the switching, the SVC model is capable of reverting back to a (larger) timestep compatible with the one used by the parent program. Other features considered include the modeling of a phase-locked-loop-based, valve firing system. An application of this model to the simulation of a SVC controlling the AC voltage of the inverter bus of a back-to-back HVDC (high-voltage direct current) tie is presented.>
Gole et al. (Sun,) studied this question.
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