Achieving high-yield heterogeneous integration in silicon photonics and advanced microelectronics requires compact, high-contrast metrology to inspect buried interfaces during die-to-wafer and stacked-chip assembly. This inspection underpins pre-bond alignment, post-bond offset verification, and defect screening, yet conventional through-silicon microscopy depends on objective optics and mechanical focusing that are difficult to integrate into high-throughput packaging tools. Building on progress in lensless computational imaging, we expand its role in the semiconductor value chain by introducing reflective-mode lensless through-silicon microscopy for packaged systems. Our module combines coherent 1064 nm illumination, a non-polarizing beam splitter reflective geometry, and a CMOS sensor; amplitude and phase are recovered from a single recorded diffraction pattern using iterative phase retrieval with denoising regularization. By eliminating objectives and moving parts, the architecture reduces footprint while preserving micrometer-scale spatial resolution. Using a USAF-1951 target, the system resolves features down to 2.19 μm under a conservative contrast criterion. Contrast-transfer analysis shows that the phase channel delivers markedly higher contrast and improved feature fidelity across the field of view, while the amplitude channel remains consistent with previously reported through-silicon near-infrared (NIR) microscopy performance. We validate application relevance by imaging silicon-photonic PICs and heterogeneous III–V/Si assemblies through the silicon substrate, resolving waveguides, metallization, chip edges, alignment markers, and bonding-related defects. In stacked-chip configurations, digital refocusing enables depth-selective reconstruction of multiple layers. These results position reflective lensless through-silicon phase imaging as a scalable, compact alternative to conventional NIR/short-wave infrared microscopy for semiconductor assembly metrology, enabling in-tool inspection and alignment verification for emerging co-packaged optics and 3D chiplet architectures.
Власов et al. (Mon,) studied this question.
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