Pseudo-System-Level Network-on-Chip Design and Simulation with VHDL: A Comparative Case Study on Simulation Time Trade-Offs

Background/Objectives: To meet the challenge of increasing design complexity, designers are turning to System Level Design Languages (SLDLs) to model systems at a higher level of abstraction. Methods/Statistical Analysis: Now there are some system level languages like SystemC but hardware developers prefer HDL based languages like VHDL for coding. So focusing on methods for extending VHDL for system-level modeling is the issue of hardware modeling researches. VHDL itself has some high level structures to model near system-level. Here we have implemented a 9 switch Network-on-Chip (NoC) with processing and communication elements like FIFOs and we have tried to eliminate signals as communication elements between processing components and using high level structures in addition to resolution function (for the first time in NoC structure) in routing algorithm. Finding: Resolution function can decrease simulation speed as in the literature mentioned so we have applied some improving techniques for simulation accelerating to see the result of these tradeoffs. All in all the one with resolution function and other high level structures besides applying improving speed rules has better performance and we have gain about 28% speed up and 35% speed up in contrast to the latter one without eliminating possible signals. Conclusion/Application: All in all by using accelerating rules we had no simulation time penalty and gained 28% speed up. Resolution function is a high level structure which is used for hardware purposes, it is preferable than simply implementing the routing algorithm by other common statements.