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June 4, 2026Sensors0 citationsOpen Access

Hardware-Efficient Real-Valued Neural Predistorter for Multimode Power Amplifiers

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LFLuiza FreireLSLuis SchuartzELEduardo G. Lima

Key Points

  • This work aims to create a simplified neural network model for predistorting signals in multimode power amplifiers.
  • Developed a real-valued neural predistortion model to mitigate nonlinear distortion.
  • Investigated two configurations: single-network and iterative cascaded structures.
  • Compared the new formulation against a complex-valued reference model for accuracy and complexity reduction.
  • Achieved computational complexity reduction by up to 34% in multiplications and 25% in additions.
  • Reduced look-up table (LUT) usage by 73.9%, making it more hardware efficient.
  • Maintained accuracy comparable to the reference model in signal predistortion.

Abstract

Digital predistortion (DPD) is essential for mitigating nonlinear distortion in radio-frequency (RF) power amplifiers (PAs), particularly in modern multimode transmitters. Among the existing approaches, the neural-network-based DPD reference model adopted in this work is attractive due to its high modeling accuracy and effective predistortion capability. However, its practical implementation is hindered by the computational complexity of the preprocessing stage, which relies on magnitude extraction, phase normalization, and trigonometric operations. Motivated by this limitation, this work proposes a simplified hardware-efficient formulation, derived from an existing real-valued three-layer perceptron (TLP)-based DPD model, for multimode PA linearization. The proposed approach preserves the main characteristics of the reference model while replacing conventional magnitude and phase normalization with a simplified feature representation derived from complex-valued signal products, eliminating square-root, reciprocal, and trigonometric operations. Two configurations are investigated: a single-network formulation and an iterative cascaded structure composed of compact networks trained sequentially. Simulation results demonstrate accuracy comparable to the reference model while reducing computational complexity by up to 34% in multiplications, 25% in additions, and 73.9% in LUT usage, making the proposed approach suitable for FPGA and ASIC implementations.

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Cite This Study

Freire et al. (2026) studied this question.

synapsesocial.com/papers/6a211743d499ed480b170116https://doi.org/10.3390/s26113503
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