Evaluating and Enhancing Performance through Macro-Op Fusion Optimization with RISC-V

RISC-V, renowned for its simplicity and extensibility, has garnered significant attention in the realm of high-performance processor construction. However, its streamlined design necessitates more instructions for tasks compared to established ISAs like armv8 and x86, resulting in increased code size and dynamic instruction counts. To mitigate this drawback, various RISC-V extensions have been proposed, yet performance gaps persist when compared to mature ISAs. In this paper, we address this challenge by leveraging the technique of macro-op fusion, a proven method in modern processors for enhancing instruction throughput and resource utilization. By fusing compatible instructions into larger, more complex macro-ops, processors can exploit parallelism more effectively, thereby improving overall performance. We present an optimization approach targeting instruction scheduling and register allocation within LLVM, coupled with a novel evaluation framework to assess the efficacy of our modifications. Through this endeavor, we aim to bridge the performance disparity between RISC-V and established ISAs, unlocking greater potential for RISC-V-based high-performance processors.