High Speed Fault Tolerant Approximate Adder for Low Power Application

This paper presents a novel fault-tolerant approximate adder based on a controlled incrementer module, designed to meet the demands of high-performance, area-efficient arithmetic units in modern computing systems. Three distinct designs-high accuracy Algorithm-Based Adder(ABA), high-speed low power NAND and NOR-Based Adder (NNBA), and low area XOR Based Adder (XBA)-are proposed in this paper. The architectures have been implemented using Synopsys SAED 90nm Design Vision platform. Post-implementation results reveal NNBA's superiority, showcasing a 67.3% improvement in power, 86.8% in area, and 78.4% in delay compared to the conventional counterparts. This underscores the efficiency of the proposed fault-tolerant approximate adders across key metrics.