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This article proposes a high-speed framed-pulsewidth modulation (FPWM) transceiver that applies a time-domain modulation scheme for increased spectrum efficiency. The achieved coding gain is 75%, indicating that the minimum pulsewidth is increased by 1. 75 times compared to an NRZ scheme with an identical data rate. Such bandwidth reduction renders dispersion tolerance both in copper and optical channels. The encoder and decoder employ successive approximation (SA) and weighted sum (WS) algorithms for power-and-area efficiency. The FPWM demonstrates an 8-dB SNR gain over NRZ at 15-km single-mode fiber (SMF) transmission while maintaining identical back-to-back performance. The FPWM scheme shows 6-dB higher receiver sensitivity at a bit error rate (BER) of 2e-5 than the PAM-4 signaling in 26-Gb/s back-to-back transmission and achieves 4-dB SNR gain at 20-km transmission. The test chip is fabricated in a 28-nm CMOS process and packaged in a flip-chip chip scale package (FCCSP). The test chip occupies 2. 2 2. 0 mm, including bidirectional two lanes and two phase-locked loops (PLLs), while it consumes 262 mW per lane from a 0. 9-V supply. The measured Tx random jitter is 265 fs ₑ₌ₒ.
Kwon et al. (2024) studied this question.