Design and Implementation of a Digital Phase Locked Loop Frequency Synthesizer in the L Band

This paper proposes a design and implementation method of DPLL frequency synthesizer system. Such a system offers many advantages such as minimum complex architecture, low power consumption, and a maximum use of large scale integration technology. It can be used in many applications as cordless telephones, rnobile radios and other wireless products. A (2.4 - 3.6) GHz frequency range is designed and implemented with a 100KHz frequency step size. A spurious output levels of -70 dBc, an output power should be greater than 10 dBm, and a phase noise less then (-100) dBc/Hz at 100 kHz ofl'set from the carier are considered in our design. The channel selection is guided by digital gating circuits with thumbwheel switches. An option of PI\4 modulation of 5 MHz FM bandwidth is also included.