Binary network design for dedicated hardware circuits

The paper investigates a binarized backbone neural network design optimization method for dedicated hardware circuits, in which the activation values and weights of the convolutional operations are represented by 1bit to achieve low computation and low number of parameters while maintaining a high image classification accuracy. The network adopts a hyperparameterized design training method, which introduces hyperparameters in the binarization process of activation function, weights and activation values to improve the accuracy, and the inference process fuses all hyperparameters absorption into two binarization threshold numbers to simplify the hardware experimental complexity. The network downsampling layer adopts a separate design, using the pooling layer to complete the downsampling task of the convolutional module, which improves the accuracy while ensuring that all convolutional layers in the network have a step size of 1, providing uniformity and convenience, suitable for hardware deployment. The input layer is binarized, and all convolutional binarization is achieved by binarizing the RGB three-channel data into 24 channels to retain the input information, and only the BN and pooling layers retain the multi-value information. Based on the above scheme, the proposed binary network model architecture has good hardware adaptability, and the computational and parametric quantities are lower than other common binary networks, while maintaining high accuracy, achieving 89.27% and 66.21% top-1 accuracy on the Cifar10 and Cifar100 Dataset, respectively. A model that maintains multi-valued information in the input layer and binary data in the other layers achieves a top-1 accuracy of 65% on the ImageNet Dataset.