Conventional Tests for Approximate Scan Logic

The approximate computing paradigm allows chips with imperfect functional logic to be utilized for computations that can tolerate imprecise results. In addition to the functional logic, scan logic is inserted into a chip to support test application. With scan logic typically occupying over 30% of the area of a chip, yield improvements analogous to those achieved with approximate computing can be achieved if faults in the scan logic are tolerated. An earlier work suggested the conditions under which a chip with faults in the scan logic is usable. Scan logic with faults that can be tolerated, leaving the chip usable, is referred to in this article as approximate scan logic. The test set suggested earlier for supporting the use of chips with approximate scan logic deviates from the test sets conventionally used for fault detection. This article addresses this limitation by describing a test generation procedure that produces a conventional test set with the following components: functional test sequences that are not sensitive to faults in the scan logic; and conventional multicycle scan-based tests with reduced sensitivity to faults in the scan logic. Experimental results for benchmark circuits demonstrate the effectiveness of conventional tests for approximate scan logic.